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Be sure to check the copyright laws for your country before downloading or redistributing this file. This eBook is made available at no cost and with almost no restrictions whatsoever. You may copy it, give it away or re-use it under the terms of the Project Gutenberg of Australia License which may be viewed online at To contact Project Gutenberg of Australia go to GO TO HOME PAGE Sir Walter Scott by John Buchan. First published by: First UK edition: Cassell & Co., London, 1932 First US edition: Coward-Mccann, Inc., New York, 1932 TO TWO FRIENDS—LOVERS OF SIR WALTER— STANLEY BALDWIN & GEORGE MACAULAY TREVELYAN TABLE OF CONTENTS • • Antecedents • Boyhood and Youth. 1771-1792 • Early Manhood. 1792-1799 • Lasswade and Ashestiel. 1799-1810 • Farewell to Poesy. 1810-1814 • The Early Novels. 1814-1817 • The Broken Years. 1817-1819 • Edinburgh and Abbotsford. 1820 • High Noon. May 14, 2017. Cannon Gas Miser Manual: Software Free Download. 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The following abbreviations have been used:— A. Constable Archibald Constable and His Literary Correspondents. Edinburgh, 1873. Ballantyne Humbug The Ballantyne-Humbug Handled in a Letter to Sir Adam Ferguson. Edinburgh, 1839. Cockburn, Mem. Memorials of His Time, by Henry, Lord Cockburn. Edinburgh, 1856. Manners The Domestic Manners and Private Life of Sir Walter Scott, by James Hogg. Glasgow, 1834. Letters Familiar Letters of Sir Walter Scott. Edinburgh, 1894. Gillies Recollections of Sir Walter Scott, Bart., by R. London, 1837. Journal The Journal of Sir Walter Scott. Edinburgh, 1891. Lang The Life and Letters of John Gibson Lockhart, by Andrew Lang. London, 1897. Lockhart Memoirs of the Life of Sir Walter Scott, Bart., by John Gibson Lockhart. Edinburgh, 1837-8. Prose Works The Miscellaneous Prose Works of Sir Walter Scott, Bart. Edinburgh, 1843-6. The Private Letter-Books of Sir Walter Scott. London, 1930. Refutation Refutation of the Misstatements and Calumnies Contained in Mr Lockhart’s Life of Sir Walter Scott. Edinburgh, 1838. Reply A Reply to Mr Lockhart’s Pamphlet, by the authors of the Refutation. Edinburgh, 1839. The Sir Walter Scott Quarterly. Edinburgh, 1927-8. Sederunt Book The Sederunt Book of James Ballantyne and Company’s Trust. In National Library of Scotland. Skene Memories of Sir Walter Scott, by James Skene. London, 1909. I have given authority for most of my references, since Scott’s own writings and the books about him are bulky works, and the reader may be glad of finger-posts. Elsfield Manor, Oxon. December 1931. 604 pages, paperback, 1.5 in. Flexible reference book format 6.9 x 9 in., perfect-bound. Printed black and white on 60# offset paper from sustainable sources. Reader-friendly serif font (Linotype Syntax 9.5 Pt.). One-column layout with numerous figures and info boxes. E-book in full color. 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Courtesy of Heritage. Next page: Rick's mentor appears in a dream sequence in Veitch's Pocket Universe: The Collected Rare Bit Fiends Vol. 2 (King Hell Press, 1995). Courtesy of R.V. Giving Back:Teaching. Immortan Joe is the main antagonist of the 2015 Warner Bros. Oscar-winning action movie hit, Mad. It charted internationally as well, peaking within the top 10 in and as well as appearing in,,, and the. My Name Is Joe contained three singles—', 'Treat Her Like a Lady', and '—the first and last of which appeared within the top five of the US. The album has been by the (RIAA), certified platinum by, and certified silver by the (SNEP). Contents • • • • • • • • • Reception [ ] Commercial performance [ ] This album was a huge success in Japan and especially in South Africa, hitting #1 for 18 consecutive weeks. It also received wide acclaim in the United States. Professional ratings Review scores Source Rating Track listing [ ] No. Title Length 1. 'Intro (My Name Is Joe)' (Joe Thomas, Joshua P. Thompson, Quincy Patrick) 0:46 2. 'Somebody Gotta Be on Top' (Joe Thomas, Joshua P. Slaughter) 4:11 3. ' (Roy Hamilton, Ernest Dixon) 3:52 4. 'Table for Two' (Joe Thomas, Joylon Skinner, Allen Gordon) 5:29 5. ' (Joe Thomas, Jolyon Skinner, Michele Williams) 4:56 6. 'Treat Her Like a Lady' (Steve Huff, ) 4:17 7. 'Get Crunk Tonight' (,, ) 4:17 8. '5 6 3 (Joe)' (Joe Thomas, Joshua P. Thompson) 4:05 9. 'Peep Show' (Joe Thomas, Joylon Skinner, Allen Gordon) 4:26 10. 'One Life Stand' (Joe Thomas, Joshua P. Thompson, ) 4:39 11. 'Black Hawk' (Joe Thomas, Jolyon Skinner, ) 4:13 12. 'I Believe in You (featuring )' (Joe Thomas, Joylon Skinner, Allen Gordon) 4:57 13. 'So Beautiful' (Joe Thomas, Tim Kelley, Bob Robinson) 4:26 14. ' [Make It Last Remix] (featuring & )' (Mariah Carey,, Teddy Riley, ) 4:11 European Bonus Tracks No. Title Length 15. 'Soon As I Get Paid' 3:13 16. 'I'm Missing You' 4:25 17. 'No One Else Comes Close' 3:51 UK Special Edition Bonus Track No. Title Length 18. 'Stutter (Double Take Remix)' (featuring ) 3:33 Personnel [ ] Credits for My Name Is Joe adapted from Allmusic. • Erlewine, Stephen Thomas.... Retrieved January 8, 2012. Retrieved January 8, 2012. Retrieved January 7, 2012. Toronto, CAN. Lescharts.com (in French). Retrieved January 7, 2012. Dutchcharts.nl (in Dutch). Hung Medien / hitparade.ch. Retrieved January 7, 2012. Retrieved January 7, 2012. Retrieved January 7, 2012. Retrieved January 7, 2012. Retrieved January 8, 2012. • (in French). Retrieved January 8, 2012. Select JOE and click OK •.. Retrieved January 8, 2012. If necessary, click Advanced, then click Format, then select Album, then click SEARCH. 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It was introduced by Zilog in 1976 as the startup company's first product. The Z80 was conceived by Federico Faggin in. The idea of being able to simulate the ASICs from the information in this documentation was so obviously attractive that were developed that could read the VHDL files. The next step was the development of tools that read the VHDL, and output a definition of the physical implementation of the circuit. Due to the Department of Defense requiring as much of the syntax as possible to be based on Ada, in order to avoid re-inventing concepts that had already been thoroughly tested in the development of Ada, [ ] VHDL borrows heavily from the in both concepts and. The initial version of VHDL, designed to standard IEEE 1076-1987, included a wide range of data types, including numerical ( and ), logical ( and ), and, plus of bit called bit_vector and of character called. A problem not solved by this edition, however, was 'multi-valued logic', where a signal's (none, weak or strong) and unknown values are also considered. This required, which defined the 9-value logic types: scalar std_logic and its vector version std_logic_vector. Being a resolved subtype of its std_Ulogic parent type, std_logic typed signals allow multiple driving for modeling bus structures, whereby the connected resolution function handles conflicting assignments adequately. The updated, in 1993, made the syntax more consistent, allowed more flexibility in naming, extended the character type to allow ISO-8859-1 printable characters, added the xnor operator, etc. [ ] Minor changes in the standard (2000 and 2002) added the idea of protected types (similar to the concept of class in C++) and removed some restrictions from port mapping rules. In addition to IEEE standard 1164, several child standards were introduced to extend functionality of the language. IEEE standard 1076.2 added better handling of real and complex data types. IEEE standard 1076.3 introduced types to facilitate arithmetical operations on vectors. IEEE standard 1076.1 (known as ) provided analog and mixed-signal circuit design extensions. Some other standards support wider use of VHDL, notably (VHDL Initiative Towards ASIC Libraries) and circuit design extensions. In June 2006, the VHDL Technical Committee of (delegated by IEEE to work on the next update of the standard) approved so called Draft 3.0 of VHDL-2006. While maintaining full compatibility with older versions, this proposed standard provides numerous extensions that make writing and managing VHDL code easier. Key changes include incorporation of child standards (1164, 1076.2, 1076.3) into the main 1076 standard, an extended set of operators, more flexible syntax of case and generate statements, incorporation of VHPI (VHDL Procedural Interface) (interface to C/C++ languages) and a subset of PSL (). These changes should improve quality of synthesizable VHDL code, make testbenches more flexible, and allow wider use of VHDL for system-level descriptions. In February 2008, Accellera approved VHDL 4.0 also informally known as VHDL 2008, which addressed more than 90 issues discovered during the trial period for version 3.0 and includes enhanced generic types. In 2008, Accellera released VHDL 4.0 to the IEEE for balloting for inclusion in IEEE 1076-2008. The VHDL standard IEEE 1076-2008 was published in January 2009. Standardization [ ] The Standard 1076 defines the or VHDL. It was originally developed under contract F33615-83-C-1003 from the awarded in 1983 to a team with Intermetrics, Inc. As language experts and prime contractor, with as chip design experts and as computer system design experts. The language has undergone numerous revisions and has a variety of sub-standards associated with it that augment or extend it in important ways. 1076 was and continues to be a milestone in the design of electronic systems. [ ] Revisions [ ] • IEEE 1076-1987 First standardized revision of ver 7.2 of the language from the United States Air Force. • IEEE 1076-1993 (also published with ) Significant improvements resulting from several years of feedback. Probably the most widely used version with the greatest vendor tool support. • IEEE 1076-2000 Minor revision. Introduces the use of protected types. • IEEE 1076-2002 Minor revision of 1076-2000. Rules with regard to buffer ports are relaxed. • IEC 61691-1-1:2004 IEC adoption of IEEE 1076-2002 • IEEE 1076-2008 (previously referred to as 1076-200x) Major revision released on 2009-01-26. Among other changes, this standard incorporates a basic subset of PSL, allows for generics on packages and subprograms and introduces the use of external names. • IEC 61691-1-1:2011 IEC adoption of IEEE 1076-2008 Related standards [ ] • IEEE 1076.1 VHDL Analog and Mixed-Signal () • IEEE 1076.1.1 VHDL-AMS Standard Packages (stdpkgs) • IEEE 1076.2 VHDL Math Package • IEEE 1076.3 VHDL Synthesis Package (vhdlsynth) • IEEE 1076.3 VHDL Synthesis Package - Floating Point (fphdl) • IEEE 1076.4 Timing (VHDL Initiative Towards ASIC Libraries: vital) • IEEE 1076.6 VHDL Synthesis Interoperability • VHDL Multivalue Logic (std_logic_1164) Packages Design [ ] VHDL is commonly used to write text models that describe a logic circuit. Such a model is processed by a synthesis program, only if it is part of the logic design. A simulation program is used to test the logic design using simulation models to represent the logic circuits that interface to the design. This collection of simulation models is commonly called a testbench. A VHDL simulator is typically an. This means that each transaction is added to an event queue for a specific scheduled time. If a signal assignment should occur after 1 nanosecond, the event is added to the queue for time +1ns. Zero delay is also allowed, but still needs to be scheduled: for these cases is used, which represent an infinitely small time step. The simulation alters between two modes: statement execution, where triggered statements are evaluated, and event processing, where events in the queue are processed. VHDL has constructs to handle the inherent in hardware designs, but these constructs ( processes) differ in syntax from the parallel constructs in Ada ( tasks). Like Ada, VHDL is and is. In order to directly represent operations which are common in hardware, there are many features of VHDL which are not found in Ada, such as an extended set of Boolean operators including nand and nor. VHDL has file input and output capabilities, and can be used as a general-purpose language for text processing, but files are more commonly used by a simulation testbench for stimulus or verification data. There are some VHDL compilers which build executable binaries. In this case, it might be possible to use VHDL to write a testbench to verify the functionality of the design using files on the host computer to define stimuli, to interact with the user, and to compare results with those expected. However, most designers leave this job to the simulator. It is relatively easy for an inexperienced developer to produce code that simulates successfully but that cannot be synthesized into a real device, or is too large to be practical. One particular pitfall is the accidental production of rather than as storage elements. One can design hardware in a VHDL IDE (for FPGA implementation such as Xilinx ISE, Altera Quartus, Synopsys Synplify or Mentor Graphics HDL Designer) to produce the schematic of the desired circuit. After that, the generated schematic can be verified using simulation software which shows the waveforms of inputs and outputs of the circuit after generating the appropriate testbench. To generate an appropriate testbench for a particular circuit or VHDL code, the inputs have to be defined correctly. For example, for clock input, a loop process or an iterative statement is required. A final point is that when a VHDL model is translated into the 'gates and wires' that are mapped onto a programmable logic device such as a or, then it is the actual hardware being configured, rather than the VHDL code being 'executed' as if on some form of a processor chip. Advantages [ ] The key advantage of VHDL, when used for systems design, is that it allows the behavior of the required system to be described (modeled) and verified (simulated) before synthesis tools translate the design into real hardware (gates and wires). Another benefit is that VHDL allows the description of a. VHDL is a, unlike procedural computing languages such as BASIC, C, and assembly code, which all run sequentially, one instruction at a time. A VHDL project is multipurpose. Being created once, a calculation block can be used in many other projects. However, many formational and functional block parameters can be tuned (capacity parameters, memory size, element base, block composition and interconnection structure). A VHDL project is portable. Being created for one element base, a computing device project can be ported on another element base, for example with various technologies. A big advantage of VHDL compared to original is that VHDL has a full type system. Designers can use the type system to write much more structured code (especially by declaring record types). Design examples [ ]. (this is a VHDL comment) -- import std_logic from the IEEE library library IEEE; use IEEE.std_logic_1164. All; -- this is the entity entity ANDGATE is port ( I1: in std_logic; I2: in std_logic; O: out std_logic ); end entity ANDGATE; -- this is the architecture architecture RTL of ANDGATE is begin O. DFF: process ( RST, CLK ) is begin if rising_edge ( CLK ) then Q. Library IEEE; use IEEE.std_logic_1164. All; use IEEE.numeric_std. All; -- for the unsigned type entity COUNTER is generic ( WIDTH: in natural:= 32 ); port ( RST: in std_logic; CLK: in std_logic; LOAD: in std_logic; DATA: in std_logic_vector ( WIDTH - 1 downto 0 ); Q: out std_logic_vector ( WIDTH - 1 downto 0 )); end entity COUNTER; architecture RTL of COUNTER is signal CNT: unsigned ( WIDTH - 1 downto 0 ); begin process ( RST, CLK ) is begin if RST = '1' then CNT '0' ); elsif rising_edge ( CLK ) then if LOAD = '1' then CNT. Process begin wait until START = '1'; -- wait until START is high for i in 1 to 10 loop -- then wait for a few clock periods. Wait until rising_edge ( CLK ); end loop; for i in 1 to 10 loop -- write numbers 1 to 10 to DATA, 1 every cycle DATA. • Department of Defense (1992).. Retrieved November 15, 2017. • ^ 1076-1987 – IEEE Standard VHDL Language Reference Manual. • 1076-2008 – IEEE Standard VHDL Language Reference Manual. • 1076-1993 – IEEE Standard VHDL Language Reference Manual. • 1076-2000 – IEEE Standard VHDL Language Reference Manual. • 1076-2002 – IEEE Standard VHDL Language Reference Manual. • IEC 61691-1-1 First edition 2004-10; IEEE 1076 — IEC/IEEE Behavioural Languages - Part 1-1: VHDL Language Reference Manual (Adoption of IEEE Std 1076-2002). • 1076c-2007 – IEEE Standard VHDL Language Reference Manual Amendment 1: Procedural Language Application Interface. • 61691-1-1-2011 — Behavioural languages - Part 1-1: VHDL Language Reference Manual. University of Southampton. Retrieved 23 February 2017. Retrieved 22 December 2012. Retrieved 22 December 2012. • Jiri Gaisler. Retrieved 15 November 2017. • 1076/INT-1991 – IEEE Standards Interpretations: IEEE Std 1076-1987, IEEE Standard VHDL Language Reference Manual. Further reading [ ] • Peter J. Ashenden, 'The Designer's Guide to VHDL, Third Edition (Systems on Silicon)', 2008,. (The VHDL reference book written by one of the lead developers of the language) • Bryan Mealy, Fabrizio Tappero (February 2012).. The no-frills guide to writing powerful VHDL code for your digital implementations.. • Johan Sandstrom (October 1995).. Integrated System Design. — Sandstrom presents a table relating VHDL constructs to constructs. • Qualis Design Corporation (2000-07-20). Qualis Design Corporation. Archived from (PDF) on 2003-12-10. • Qualis Design Corporation (2000-07-20). Qualis Design Corporation. Archived from (PDF) on 2016-03-14. • Janick Bergeron, 'Writing Testbenches: Functional Verification of HDL Models', 2000,. (The HDL Testbench Bible) External links [ ] Wikimedia Commons has media related to. The Wikibook has a page on the topic of: • •. By July 11, 2013 6:00 am UTC • • • 0 Like most engineers, I was first introduced to FPGAs () in college. By that time I was already experienced with programming, logic and circuit design, but even with those subjects under my belt, I found FPGAs wildly confusing. For a long time after taking that FPGA course, I was convinced that I could have developed a better course than my professor, and blamed most of my initial confusion on that. I felt that way right up until I tried to do exactly what my professor did: teach FPGAs. On the surface, it seems like someone with lots of microcontroller experience would have no problem migrating to the world of programmable logic, but that is simply not the case. Even the most experienced programmer and developer will have problems understanding the concept behind things like “.” Just the concept of a circuit being “written” in a language like VHDL rather than built is enough to confuse the average DIYer. As an engineer at SparkFun, it is my job to provide the “shortcuts” that a hobbyist or student might need to accomplish their goals in the electronic realm. So awhile ago, I set about trying to write a tutorial that would provide the base information and tools needed to get someone started using FPGAs. After ten pages of writing, I realized that teaching the concepts needed to understand and use an FPGA is a much bigger problem than I anticipated. In fact, it’s such a large and complex problem that, after a couple of years, I still haven’t found a complete way to introduce the uninitiated to the world of FPGAs. The Mojo V3 Luckily the DIY world has lots of very talented people working on the very same problem. In particular, Jack Gassett, the creator of the, and Justin Rajewski, creator of the have done the some great work creating boards and material to ease the transition into the world of FPGAs. Papilio Pro LX9 Both of these boards have a great deal of supporting information and tutorials that make them a perfect choice if one has a bit of electronics experience and wants to start working with FPGAs. The Papilio has tutorials at the site, and the Mojo has tutorials at the site. Now, I don’t want you to think that this post is meant to be an advertisement for these two boards. They’re great devices, but this post is meant to shine light on a massive gap in the open source community. To this day FPGAs are still very, very, difficult to learn and teach. There are people who want to learn logic and FPGAs that are turned off of the subject because the barrier to entry is still so high. It’s the open source community’s responsibility to lower that barrier to entry, but so far, it’s still high enough to scare away even seasoned electronics enthusiasts. So what’s to be done? Personally, I don’t really have a good answer. People like Jack Gassett and Justin Rajewski have bravely taken up the cause of bringing FPGAs to the masses, but there is still much to be done. It will still be a while (or never) until FPGAs are as friendly as, say, the Arduino, but with enough talented geeks attacking the problem, we can at least make programmable logic less scary. So what do you think the next step is? What would make FPGAs easier to learn and use? If you’re already a developer, what made your learning experience easier? Working in the FPGA industry for 2 years, I always learn something new every day. To really learn FPGAs well, you really gotta start with the very basics. Logic blocks/designs, and then translate those basic blocks into HDL (Hardware Descriptive Language) code. From here, it’s not really about learning the FPGA itself, but more on the software that you need to use the program the chip. As people in the IRC channel know, I am more than willing to demo HDL and the FPGA design process using my Justin.tv account. People that watch do learn things, and I try to make it as interactive as possible. I’m there to teach people, not do marketing demos. I personally think that Sparkfun should do something like the SIK, and do the SFIK (Sparkfun FPGA Inventor’s Kit). Where you start off with the logic block boards, then go to a Papilio/Papilio Pro/Mojo v3 board. I’m a bit biased being an FPGA designer myself, but I think getting FPGAs out there would be awesome. They are incredibly powerful pieces of hardware. Think of them as having the potential to be 100,000+ core processors which happen to run Finite State Machines rather than Machine Code. From my experience I think there are 4 major barriers to FPGAs: 1) State Machines. I know a lot of us know what they are, but for someone coming into digital through Arduinos they are a key piece that gets missed. I think a basic course in digital focusing on discrete logic would help. Ultimately that is all an FPGA is really. I would suggest a class/tutorial that goes through State Machines and how to build logic with discrete chips would help. That is how I learned, and I constantly find myself doing mental comparisons of what is happening in code to what we did with discrete logic. Maybe Pete could give us a video on FSMs 2) Parallelized Hardware Coding. FPGAs are a totally different beast when it comes to programming. I learned the basics in my Digital Logic class using the Altera schematic editor. This lets you drag and drop in basic logic blocks and wire them together. Once you understand how to build a circuit with FSMs like in number 1, then FPGA design with a schematic editor tool fairly easy to grasp. Then once you get the hang of wiring together blocks, you can start converting some or all of it to code, and see exactly how the circuit becomes code (at least I seem to remember being able to do that). I think something that may help break the programming barrier would be something like an open source library of little code blocks (like the massive amount of example code that is available for Arduino). This would let people grab say a UART or a SPI interface, and drop it into their design saving them the expertise needed to do more complex tasks. Learning to wire together code blocks, and begin to modify them to do what you want is a great way to ease into the FPGA world. That is basically how I went from absolute noob to an FPGA designer, was working with predeveloped code and breaking it down and piecing it together. I know a lot of people are getting into SMD soldering, but FPGAs tend to be relatively fine pitch, and have a ton of pins. This is kind of a turn off, especially if you want to try prototyping. I think one solution is something similar to your old Spartan 3E dev board. A basic FPGA that can easily be integrated with a breadboard design. Be sure to have a good interface to the PC though. FPGAs don’t tend to come with USB drivers, so maybe an open source JTAG adapter or something would really help. I agree tools aren’t readily available, but I really don’t think anything can be done to fix that. To build an FPGA image you are going to need the proprietary software from the manufacturer to map your logic into their device. Perhaps the best thing here is to pick an FPGA which has freely available tools (I use Xilinx ISE for example) and work up a tutorial video that shows people how to do the basics, without worrying about details they don’t need to know. For the more computer savy out there, don’t forget that most all of the tools can also be run at the command line with scripts. That can make things a lot less painful. Maybe provide a simple Makefile that will make compiling an FPGA as easy as typing ‘make’. Finally, for beginners maybe a simple development GUI to work with the code blocks I mentioned above could be written. Something basic that would let you drag and drop circuit blocks and then export the code, or simply call the real tools from the command line in the background would make things a lot easier. Just my 2 cents, not sure if they are worth that much or not. State Machines are really popular, but you can’t rule out the pipeline designs! • Schematic design after learning FSM can be difficult. Because you need to have your states generated in the schematic editor. For those “blocks”, OpenCores has them. The problem with OpenCores is the lack of documentation, and how to use them properly. Xilinx has the IP Integrator in Vivado (can’t use with the Mojo or Papilio), but it allows you to do this. • The older generation of FPGAs are all SMD, but when you get to the newer/bigger chips, they are all BGA. FPGAs have a lot of IO pins. • I agree the proprietary tools ar ethe better way to go. I know Xilinx has “Quick Take” Videos which show you how to use Vivado (not sure on the ISE side). In reality, drawing up a schematic and block diagrams by hand and not in a computer will be just as effective as SketchUp. All valid points. I studied Operations Research and some CS and my first few years in industry were as a programmer. I got interested in electronics as a hobby about 2 years ago and developed some decent microcontroller skills, largely thanks to SparkFun. A few months back, I decided that I wanted to see what all the FPGA buzz was about and I was lucky enough to get in on the ground floor with the Mojo as a kickstarter supporter. I won’t say that it was easy - the shift in thinking from writing traditional code to designing ciruits in Verilog was headache-inducing at first, but the tutorials and example code on the EmbeddedMicro site really helped to illuminate things for me. My first project was a simple scrolling display on an 8x8 LED matrix. I’m not sure whether I did it “right”, but it works. The 50 Mhz clock speed of the Mojo leaves plenty of cycles for PWM, scanning rows, and scrolling the text very smoothly and evenly. I implemented a simple RAM block to hold the characters and a second block to hold the message. My next step is to wire up a serial connection via the on-board microcontroller to display any message input on the serial port. The Mojo takes a lot of the annoying logistics out of the way so that you can jump right in and start using the FPGA. The tutorials walk you through getting the free ISE WebPack design software from Xilinx, and EmbeddedMicro provides a Loader program that uploads your finished.bin file to the microcontroller which “programs” the FPGA, all seamlessly. I had Hello World (i.e. An LED tied to a button) up and running within minutes of getting the software stack installed. I highly recommend the Mojo as a first step toward understanding and using FPGAs. If you want to learn how to design using FPGAs you could always have a crack at my informal FPGA course - The learning curve is still quite steep - “Programming without loops? WTF!”, however it is a lot less steep than doing it alone. You have to remember you are trying to make something useful out of half a million logic gates, and have it all work at tens or hundreds of megahertz. That would take the resources of a large company in the 80’s or 90’s. You can also find some of my tinkering at •. I have almost no college experience, know very little about how to use an FPGA, BUT I feel they’re super easy to understand. You just have to learn binary, then learn how shift registers & memoryworks, as well as the physics of it so you can imagine the electrons moving around like you’d imagine parts in a machine. Then you learn about logic gates, I took a digital logic class and aced it because i looked it all up already, did learn you can’t leave any pins floating though. And then from there, you watch a video on youtube calles ‘how computers add numbers, in 10 easysteps’ or something like that, repeat until it’s understood how logic gates can perform mathmatical operations. I imagine knowing how a processor works might be helpful, pick one you might want to be an expert on and read the manual over and over until eachlittle part you manage to understand link together, they don’t write those manuals for noobs so it’ll take a while to understand. Then, just realize an fpga doesn’t use a clock unless you add one, it’s basically logic gates, and you should know from learning about logic gates how each gate can be translated into a mathmatical operator. I imagine programming an fpga is all about the syntax of connecting pins to formulas, and the compiler takes care of routing all logic blocks. Something like that. I see look up tables on fpga specs (designing a circuit that uses an fpga) and i imagine those allow saving resources by simplifying complex calculations that have few possibilities, in order to increase resource efficiency. Justmy guess. Zero college, I read textbooks on electricity and it confuses me, i haven’t even taken precalculus and they expect me to know derivatines, differentiation, integration, symbols i don’t even know how to look up, confusing stuff. My brother is taking a basic electricity class, while I’m designing a switched mode power supply. Iask him what they’re teaching him because I’m curious about what I’d learn if I went to college. Dependant/independant voltage/current sources, nodal/grid analysis, I can’t even understand the descriptions of this stuff really, college overly complicates things and pushes useless info. They have it worded in ways robots might understand well (correct & strictly worded syntax), but not people. I personally love fpgas despite not knowing how to use them, I think they’re superior to processors in most applications. Our brains surpass computers, and work using neurons, which is like a cluster of logic blocks and connections. Kinda want to build an fpga based computer, it’d make game/os emulators so much better if you can just switch archiatecture like that. Behavioral or Structural? VHDL is my favorite, structural way is for hardware oriented people while behavioral is for software inclined. I had once an encounter with FPGA’s, while i was designing a crypto block in vhdl. I preferred the structural way as it was closer to how components are physically interconnected in hardware. Hardware equivalent of an “ conditional if statement” is the multiplexer. It is possible even to transform C/C++/C#/Vb like languages to pure VHDL, just by reading line by line c like code and jumping along goto line. OK - good news - I know this is a bit of an old blog, however I visited Xilinx in Ireland this week (March 2015) and they have developed a more used-friendly c-like interface which is designed to directly address the difficulty in using FPGAs - plus the lack of Verilog-trained engineers today. Vivado HLS (uses C/C++) SDAccel (uses OpenCL) definitely worth a look - should allow us more menial “c folk” to understand & use FPGAs. As a new learner with a variety of programming background and a specialty of none:). I think by just reading over the comments here I feel more confused than I think I should be. So if I’m right how others in the learning curve might feel I’d start with a super basic overview understanding that relates FPGAs to hobby electronic devices that are more commonly known. Perhaps a learning model approach, like. 1) An FPGA; by all means, is an electronic breadboard and/or Generic PCB with selectable digital components; all inside a single chip. 2) Just as one wouldn’t give a breadboard a list of instructions (like PC-programming) FPGA’s don’t take a sequential list of instructions. Instead they take a list of wiring connections (IE. A) FPGA chips are like an ASIC(Application specific IC) manufacturing plant at your finger-tips. It is very true to say that digital electronic circuit (or IC) designers use FPGA's heavily during ASIC design and the decision to release that circuit design implemented on an FPGA or ASIC; is for the most-part entirely cost comparison driven. 3) The concept of programming (Really better named “circuit designing”) with an FPGA is often confused because EDA(Electronic design automation) tools use a PC-Programming like method to “Automatically-Create” the circuit (IE. The wiring connections and digital components) for you via abstraction methods; Verilog/VHDL; instead of having you pick and wire them together discretely. A) And as a reflection of this model; Verilog/VHDL has different “levels” of abstraction one can circuit design. Be it “Structural” for just stating which components to use and wire them together or “Behavioral” where one describes the intended circuits functionality and letting the EDA-Synthesis tool derive/determine how to wire together the circuit to produce the behavior you’ve described. I gave a power point presentation last night to our robotics club about FPGAs. My big point was that it is not CPU vs FPGA, it is CPU + FPGA. I have been around the industry for a lot of years at www.srccomputers.com, I have worked with both Xilinx and Altera products. At the moment, my preference is Altera tools and verilog language. I have eval boards for both zynq7000 and Cyclone V ST right now and I love the SoC concept(these are similar offerings from both companies with ARM core plus programmable logic). I am laying out a PCB for hobby UAV that uses the Cyclone V ST. My tact is to show what the chip can do and what the cost is while developing ways to bring new people on board. After giving some examples of what is possible with these new SoC devices, the last bullet says “These are more complex to work with, but I can teach you.” And now we come full circle to the article, there are a lot of concepts to learn for FPGA design. However, if a nice website builds on the curriculum then the core does not have to be completely hashed out with every new person. In addition, free FPGA classes can help with hands on learning. I designed a 1Ghz logic analyzer with little more than an Altera FPGA and a serial port. Try that with your latest processor of the day, I don’t care if you can program in CUDA and all that–FPGAs and processors are simply different tools for different jobs. I designed an FPGA interface for the Raspberry Pi that uses direct writing of RPi GPIOs to achieve about a 16Megabyte/sec transfer time in C (don’t use the BCM2835 library functions, that will limit you to around 2.5 Mbytes or less). This overcomes some of the limitations of the RPi by putting in a precisely timed thread scheduler, touch panel HW, 64 high current IOs, and an LVDS LCD panel interface in the FPGA. I’m working on an FPGA design that will take HDMI signals (10 samples per clock) to LVDS video (7 samples per clock) so that the RPi video can be displayed on the panel. None of these are practical things for a processor to do. It’s a giant circuit sandbox, and the tools are getting better for makers. I’ll brag a little and tell you I’ve been doing this since 1978, when I designed what could arguably be called the world’s first FPGA in college (I still have all the project data, and I got an A+!) using rectangles to draw out transistors. Somebody said FPGAs are going away, I laughed, they are just now coming into their own •. Texas Instruments was the company that paved the way–they were the true innovators. Signetics, Intel, AMD, Motorola all were nascent in the new IC business as well. Xilinx and Altera came along quite a bit later–it took a really long time for the configurable logic concept to be really workable. I remember being so excited about the IC stuff anyone could buy for the first time–I was the only one in my high school of 3000 students doing anything in the IC electronics building area! When I was in college, IC logic was available in increasing complexity, but the notion of configurable logic didn’t really exist as far as I knew–somehow I came up with the idea of reconfigurable logic (and hence my college IC project). At the time, I’m sure others had ideas about configurable logic as well–but it took a very long time for the notion to become remotely as good in practice (as fast, as cheap, as reliable) as wiring up existing ICs. I made an array of interconnected nand gates that were selectivly enabled by a small array of nand latches. Depending on how you wrote the nand latches, you could alter the input to output function of the IC. Pretty simple, but those were amazing times where you really could come up with ideas never been done before. I knew several people that went on to be very successful in the tech business, but I had (and still don’t) no interest in money-making or business–I’ve just always loved making things, so I maybe had opportunities but never took them. I’ve had a long and mostly comfortable career in logic and ASIC design, and that was good enough for me. Getting back to the subject, FPGAs are the ultimate playground for somebody like me–processors can’t touch the flexibility of what can be done here. Woah, woah, woah, pump the brakes on mis-information. Texas Instruments was not a front leading company. Fairchild was the inventor of both discrete logic, and modern transitor, but most famously the integrated circuit, to which now everyone uses. TI sued them when they came out with the IC because TI was still using discrete circuity. Fairchild got super greedy, didn’t pay the employees well, didn’t innovate, and ultimately was hazardous to the mind. The lead designer (IC inventor) years later quit, and took the people he liked and started.dat dat dah.Intel. Which then created the first.Microprocessor, and literally birthed the chip of the computing future. Welcome to real history, not some stupid, false corporate dogma. Side Note: AMD invented the first 64-bit cpu during the 16-bit era •. I think FPGAs are probably pretty scary to program, but then the only experience I have is that my high school electronics class did some stuff once with GALs which required boolean logic ex. (A && B &&!C)|| (!A && C)||!B That was terrifying painful, I couldn’t do it today even if I had the equipment although I think we did manage to make it work. Translating an idea into logic like that is a headache. Hopefully it’s nothing like that. I suspect one big barrier is that you need to know a lot about logic beforehand and have a good grasp of that and how to reduce ideas to logic. I bought a DLP-FPGA USB Xilinx 3E-based FPGA Module with a very nice instruction manual from and followed their tutorials. Worked for me. The folks at DLP were very good in answering all the questions I had. The board is fitted with an FTDI part with 2 logical USB ports which means that you can create some VHDL (I’ve never tried Verilog) to send logged data back to a host PC and also program the FPGA via a single USB cable. I also used the high speed version of the board which is fitted with 32Mbytes SDRAM. Learning how to create a memory controller block using the Xilinx ISE wizard took a lot of time but was well worth it. I eventually used the module, with the SDRAM acting as a frame buffer, in a battery-powered design to control the backplane of a custom-built LCD. FPGAs are very different beasts to the MCU’s on Arduino’s and require a whole different mindset before you can start getting to grips with them. They are definitely not suitable for “whack-it-in” engineering prototype tasks like the Arduino is. • Start with why FPGA’s are needed from a practical sense. That means compare them to devices like some of the common PIC and Atmel families that have some juice. • Build upon item 1 by showing what you can’t do or what you can do better with a FPGA version of the common DIY boards such as the Arduinos, Beagles, and some of the PIC versions. • Take a common but complex project that is done with an Arduino, break it down into high level blocks and those into lower level blocks. Then do the same for how the FPGA'er would tackle the same task. I ordered a guzunty (Google it) which is a CPLD board which attaches to a Raspberry Pi. (Still waiting on shipping to deliver; ~$25 US including shipping from the UK) CPLDs are like small FPGAs (hundreds of gates instead of millions) and are also programmed with VHDL or Verilog. The Pi attachment means that I can do most stuff with Python on the Pi, and do appropriate things with VHDL on the CPLD. I could write a stepper motor controller with ramp-up/ramp-down acceleration for the CPLD that responds to register values sent by the Pi and not have to worry that Linux is not a real-time OS that can’t do the pulse timing properly.) Sparkfun doesn’t sell any CPLDs, but breakout boards are available from other vendors if you don’t want to go the Guzunty Pi route. I have never tried to ‘program’ an FPGA, but I did just learn how to program a PLC in ladder logic. I have programmed many things in basic like languages for years as well as programmed ucontrollers for several projects. The shift to programming a machine in ladder logic was fairly big. You can have several parallel process running and it ‘seemed’ much more difficult to “control” what was going on. As I learned more and more, I found that it was much easier to add certain types of functionality with ladder logic since I knew that bit of ‘code’ would alwys run regardless of what else was going on in the ‘program’ Bottom line is that ladder logic (similar to what I understand about VHDL, etc.) IS a pictorial view of hardware that used to exist as switches and relays. I’m not sure of the hardware used inside a PLC, but the implementation of programming it is very different from traditional line by line code. Some may call it BAD, but I just call it ‘different’. I agree that a lot of people try to get into FPGAs thinking that they are just supped up microcontrollers and that is simply not the case. They are far closer to a cpld (complex programmable logic device) than they are to a microcontroller. I find that the way I solve problems is much more in line with VHDL than with a traditional procedural language. I recently wrote a pong game on an FPGA for school and I found that while it was harder than doing it in Python or something like that, I liked how I could solve the problem more. On a processor I have to worry about when I do each thing and if I have enough clock cycles to get through the gameplay math so I can update the visuals. On an FPGA I can solve each issue independently. I can make some signals that represent the players and then write a different bit of code that continually displays them and another that moves them. They all get synthisized to separate logic circuits that inherently run all the time. Think of it like building a circuit with code. When I first started using FPGA’s in 1992, using VHDL was an expensive alternative. Using schematic capture was the way I originally chose to enter in designs. Xilinx had a program that would translate the netlists and then would route the fpga from that. It was kind of funny, back then it took close to 45 minutes to route a 3,000 gate fpga. I used this method until about 2002, when I switched to Verilog. For me, the transition was fairly easy. I thought of the verilog more as a verbal description of a schematic rather than a programming language. I also do a lot of programming in C/C++, but I have always been able to keep my mindset for these two activities separate. By the way, is Sparkfun going to carry the Mojo? I at the very least would find this a very handy board. I’d be curious to know more about the relationship between FPGAs and ASICs. I mean, I know what they are and such, but never having designed either I’m curious how they relate. Specifically, ASICs have been getting a lot of press in the Bitcoin world of late, and I’ve heard that one approach to designing an ASIC is first to implement the design in an FPGA and then migrate that same design to the ASIC. The idea that the two technologies would use the same description language is something I had not considered. It seems plausible, and if this is really the way it’s done then it makes learning FPGA design a lot more attractive to me personally. Plus that Mojo board is dead sexy, so there’s that. And as far as the verilog/vhdl side there are free tools out there that run on linux and windows that any one can dive in and start using. Understanding that you dont need to see an actual led light (or actual smoke come out of the part) to learn something, you can do huge, complicated designs, just like the professionals do it. That last step of taking your design to silicon has a learning curve sure, but you can divide those learning experiences up on these natural boundaries. I have been working in the silicon industry for years and along with the pay-for tools we use the free tools quite a bit (verilator and icarus and gtkwave), as we do our software development on chip/board simulators so that when silicon arrives we are mostly ready to go. I dont see the logic is all that hard, counting from 0 to 1, AND, OR, NOT covers about 99% of it. The tools are proprietary and generally not at the quality of the equivalent software toolchains. That is a major barrier to entry for software folks to transfer over. Xilinx or someone did a study back when languages were taking over schematic capture, and software folks were preferred over electrical engineers for doing logic design because all you had to teach them was the concept of things happening in parallel, they already knew programming languages and compilers and other similar tools. Today of course that is different. If someone were brave enough to make a programmable device where the guts of it, were open such that the open source community could make the compiler and place and route, etc, you would eventually see tools that dont suck, run everywhere, and overall better experience. The real reasong for adding a coment though is that if you go over and look at what xmos.com has, which wants to be competition for cpld and small fpgas, that may or may not be a good stepping stone for software folks that want to do more than just bit bang some gpios. Not the same languages, sure, C and asm instead of verilog and vhdl, not the same experience necessarily as pure logic, but the experience of understanding the signals you want to send or receive, using a simulator that provides waveforms that you use gtkwave or something with, that is all the same experience as with cplds and fpgas. I will have to poke a hole in open sourcing FPGAs. • Chip design and layout is very tough, time consuming, and very expensive. (Typical tapeouts of chips go for a few million dollars). • Place and Route algorithms come in all shapes in sizes. So when you start adding in the hundreds of variables of how to do it on a chip, it makes it very difficult. • Process nodes (110nm, 90nm 60nm, 45nm, etc) are being phased out and a lot of fabs are retiring from doing specific nodes. With these three thoughts, could someone open source it and let people make it? Sure, but it’ll take a lot of capital and a lot of work to get something out there where they don’t see a dime! I will fully support anyone who wants to do this, just know the obstacles. The best implementation I saw of an open source FPGA was multiple chips. One board of this design was one SLICE of an FPGA. As for the software programmers need not to learn the hardware. I have to say, they need to learn the guts in order to get the solution they want. I teach digital electronics (PLTW for those of you in the know) in a high school and FPGA boards comprise part of the course. We don’t get into the HDL much at all, which is auto-generated from their logic designs in Multisim. I have them look at the VHDL a little, however, which helps them to appreciate what brings their simulated circuits to life on actual hardware. I think this is a great entry into this great world of FPGA development, and I believe NI has a 30-day trial version of Multisim as well. Good on you for teaching a value set of skills to a device that gets no attention until late in everyone’s college career. May I suggest a way to help introduce HDL into learning? Relate HDL code to the digital logic circuits they’re building. With this, you can apply syntax of HDL as an afterthought and the kids should understand the do’s and dont’s of HDL. If you can say, “See this counter we built with logic devices? Let’s code it using HDL for an FPGA and see if the results we get are the same.” •. I’m in the same boat as many FPGAs are all over, but I don’t really fully understand them. Ironically, I use them constantly! And, my case is probably a good example of how they are becoming pervasive while removing the difficulties in implementing them You see, I use National Instruments Compact RIO controllers for specific control applications, as very high speed replacements to old PLC technology. The interesting thing in the cRIO is that it has an FPGA backplane built into the unit, which you can directly access and leverage when programming in LabVIEW. So, I can take my LabVIEW program, pick specific routines or code that would benefit from running at FPGA speeds (and experiencing true parallelism for execution), and just make a few conscious tweaks or planned adjustments while creating the code. When I deploy my code into the controller, it handles all of the direct programming and configuration of the FPGA, and I don’t have to think about it. It’s like some kind of cyber-magic And the speed bump in the processor that I get by pulling those functions out of the CPU and right into the FPGA can be amazing! I think, if more and more programming and development platforms can make it easy and seamless to integrated FPGAs, they will continue to grow and become even more pervasive. Sometimes, the trick is to just make tools to let people use them, without having to understand them. I mean, how many people actually know how a computer CPU works, vs how many people use one every day? Or how many circuit or board designers know the specifics of how every chip they are using works, as opposed to just knowing the functionality and general specs? It may be that a little less hardcore understanding of the intricacies of FPGA and a little more “ignorance is bliss” could make many lives so much easier Heh •. Valid points. But the thing is, FPGAs are used in extremely complex designs, which requires a lot of very specific knowledge of EE concepts. The thing that the Mojo and Papilio do is get a cheap DIY system into the hands of people willing and wanting to learn. As stated in one of my comments, the best way to learn the FPGA is to learn the building blocks (AND/OR/NOR/NAND/XOR/etc. Gates, Flip-flops, LUTs, etc.). After you understand the basics, if you can translate those to HDL. This way you have a 1:1 mapping on the code. From here, there are two things you can do: 1) Learn the features of the FPGA (very advanced), or 2) Learn the tool chains used to program the chips. I would recommend 2. This gives you the best ability to understand how to fully utilize the FPGA. I will be more than happy to do livestream on demand for anyone who wants to learn. Yep, FGPA’s are hard. You are working at the absolute lowest level of computing hardware possible. It is equivalent to connecting 74LSxx parts with jumper wires on a bread board. Add to that the fact that timing matters immensely and you have a complex, and difficult to learn environment. Learn async digital logic. Learn synchronous digital logic. Work your way up the ladder. When you understand why most FOR loops in Verilog cannot be synthesized, then start more complex stuff. Sometimes concepts are hard for a reason and not everybody gets them. Sometimes, something that looks cool takes a lot of work, maybe more work than you want to put into it. That’s ok too. In reality, if you are looking for high level programming constructs to put down large blocks of functionality on an FPGA, you don’t don’t need and FPGA. You need a microcontroller. I am a software engineer, with a master in CS. I am dabbling in electronics as a hobby. Understanding the “non-procedural” part of programming FPGAs is not all that tricky - if you have used languages such as Haskell or Prolog and encountered declarative programming during the computer science education, you would be right at home with Verilog or VHDL. Unfortunately a lot of software engineers didn’t have these things at the university, not to mention people who learn a bit of Javascript or PHP and think themselves programmers I think the worst thing someone can do trying to teach/learn programmable logic to software people is to: a) say it is programming b) say that Verilog is similar to C Neither is true in the way software engineers understand these terms and it sets the stage up for a major problem with due to not speaking the same language. It is similar thing like programmable voltage references - it took me a while to realize that “programming” them actually means soldering one or two resistors! Software engineer thinks programming = source code/compilers/execution flow and the confusion happens right there before even getting to the substance of the discussion. What makes you think I havent tried it? I’ve worked in HLS companies for the past 5 years, and am well aware of the various solutions on the market, as well as the history of companies that didn’t make it. HLS is no where near “solved”, and especially not by Vivado. The biggest strength of Vivado’s HLS is integration with backend synthesis and the rest of the toolchain. Yah, thats a huge deal, and it will probably be the HLS of choice for plenty of people for that reason. But its not really an amazing HLS solution, its a decent one that cleanly integrates into the tool chain that most people use. Sat Jun 26, 2010 6:53 pm. Animeking wrote: Default How to use Easyusetools 10. PNA users must copy file 'ttsystem' or 'PNDNAVIGATOR' also into this folder. What does step 10 mean? Your 930 doesn't use the pndnavigator file, so disregard the reference. BTW keygen 4.1D is the preferred patching tool. Apr 17, 2012. Also have a look at the new keygen tools, referenced below. 2 a file Meta.txt, with encryption information about the map. It comes with the tools. If the Meta.txt it is out-of-date (due to new maps): TTuser frequently updates the EasyUseTools, and Albert's tool has special functionality in his tool to get the latest. Ah, see if this link works, this is Western & Central Europe 840.2562 the one with ALG and EQ routes. Western_and_Central_Europe_840_2562 by Protect My Links. Com (you will need a 4 gb card because this is just over 2 gb. You then need to crack the map before it will work to crack the map you need 1 the map Western_and_Central_Europe_840_2562 by Protect My Links. Com (2 the keygen. Digital Kaos - Downloads - Easy use tools (3 meta.txt file here Digital Kaos - Downloads - meta.txt (http://www.digital-kaos.co.uk/forums/downloads/satellite/13/meta-txt-1057/). Well the good thing is your navcore is good to go with the new maps, most people have to upgrade this for the maps to work. The bad news is, I have never used easyusetools, so I cant help ya much. I crack my maps using command prompt, I need to write up a guide, as best I can to be able to post it. But I haven't done that yet. Good news is, you have all the files required, and running easyuse tools should be straight forward, you just enter the files, and info that it requests. You will need your device id too. A ten digit code looks like this AQ2TH ASDFR When you enter this, make sure you DO NOT put a space between the characters. This info is for tomtom standalone units, I am assuming the in built is the same. You only need crack the map, so all this can be done in a card reader. I will try look out for a tut for easyuse tools. Alright integra. The first thing, I am assuming your gps is the same as any other tomtom, I have never seen the inbuilt ones of Renault, but looking at the navcore, it seems to follow suit. Your navcore, 8.841, should be good to for any map, but I have never seen that version before. So the only thing you need to crack is the map. As i said to crack the map you need 1 the map Western_and_Central_Europe_840_2562 by Protect My Links. Com 2 the keygen. Digital Kaos - Downloads - Easy use tools 3 meta.txt file here Digital Kaos - Downloads - meta.txt you also need your device id, the 10 digit ABCDE FGH2J This can be be found in your tomtom by pressing sat signal, then navcore, then go about cracking the map on a fresh card, in your card reader. Just follow what easy use tools asks you for. I've tried to copy the SD card, from a original one and do not work. If you format the copy card in FAT16, then insert on the GPS, turn on the car, and wait some seconds.You will see a message, your card is ready to use on tomtom home. Now, open the card and you have a folder with a file. Edit the file and you have all the gps information, as well the card serial number. I believe the Carminat Tomtom make use of the serial numbers from the cards, why? I tried before to use the original card in a couple of diferent cars, and allways works, with the copy card, not really. I believe there is a file with a matrix, including the allowed serial numbers.that why you can buy a empty carminat tomtom card on the tomtom shop, and says, use only in carminat systems. Anyone have ideas? I'm starting to get empty! 1.) You need a patched version of Tomtom software - it will not work with the genuine software. If you are using a software version earlier than v8.010 it can be patched using the 'RunMeforAllAutomatic'. 2.) Copy new map folder to Tomtom (can also copy file named ' MapSettings.CFG' from old map folder to new map folder, this will keep your Home & Favourites locations). 3.) Make a note of your DeviceID - this is a 10 digit code eg. Open the document named DeviceID using notepad in the keygen folder and enter YOUR DeviceID code (NO SPACE) then save. 4.) Leave Tomtom connected to PC & on PC click on 'RunMeforAllAutomatic' in the keygen folder. 5.) You will see this:- Enter 1,2 or 3 for your Choice, Standard is 1 1. Run it for Navcore 8.010 and higher 2. Run it for Navcore 7 up to 8.002 3. |
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